Ishraq Tashdid

Graduate Research Assistant — University of Central Florida (Jan 2024–Present)
Hardware Security & Trustworthy Computing Lab, advised by Dr. Sazadur Rahman

• LLM-driven threat modeling & automated vulnerability reasoning (DAC 2026): Built ATLAS, a framework that ingests CWE/CVE/CAPEC vulnerability databases, auto-generates structured threat models for any SoC asset, and translates them into formal security properties verified by JasperGold. Detected 39/48 known CWEs across three HACK@DAC benchmarks (>82% correct property generation). Conducted in collaboration with Jonathan Valamehr (Intel Research), and subsequently presented to Intel's AI research community at the Intel AI Forum (Feb 2026). Directly applicable to firmware and software vulnerability workflows that reason over the same threat taxonomies.
• Automated security property generation & cross-abstraction analysis: Developed pipelines combining static analysis, AST-level structural reasoning, execution traces, and formal verification feedback to generate precise security assertions with minimal human effort, reducing reliance on manually crafted security rules at every abstraction layer from RTL through system firmware. This work forms the analytical backbone of both ATLAS and subsequent cross-abstraction security projects.
• Chiplet authentication via PUF and MPC (HOST 2026): Designed InterPUF, a distributed authentication framework for reconfigurable System-in-Package (SiP) interposers. Embedded a differential delay PUF in the interconnect fabric and secured evaluation using multi-party computation (MPC), ensuring raw signatures never leave the device. Achieved <0.23% area and <0.072% power overhead; ML modeling attacks converged at ~47% accuracy (random-guess level), demonstrating resistance to state-of-the-art ML-based reverse engineering. Addresses supply chain integrity concerns in multi-vendor chiplet ecosystems flagged by the CHIPS and Science Act (2022) and DoD supply chain security reports.
• Routing-based PUF authentication (GOMACTech 2026): Designed RoutePUF, a routing-based physically unclonable function for secure interposer authentication in chiplet systems, extending the PUF-based authentication line of work to a government/defense-microelectronics audience via the Government Microcircuit Applications and Critical Technology Conference, a forum jointly sponsored by the U.S. Department of Defense.
• Adaptive logic obfuscation for SoC IP protection (ICCD 2025): Developed ECOLogic, a framework enabling circular, obfuscated, and adaptive logic via eFPGA-augmented SoCs. The approach allows post-fabrication logic reconfiguration to resist reverse engineering and hardware Trojan insertion while maintaining functional correctness and low overhead.
• Macro placement automation (MLCAD 2025 — Best Paper Nominee): Designed human-inspired reinforcement learning frameworks for chip floorplanning to improve post-route routability and reliability in heterogeneous SoCs. Demonstrated that incorporating human design intuition into RL reward modeling yields measurable gains over PPA-only optimization baselines.
• Scalable chiplet trust architectures: Developed SAFE-SiP (GLSVLSI 2025) and AuthenTree (PAINE 2025), two complementary MPC-based distributed trust frameworks addressing authentication scalability in chiplet-based heterogeneous integration. AuthenTree achieves logarithmic communication complexity in the number of chiplets, enabling practical deployment in large-scale SiP designs.

XPU Security Research Intern — Intel Corporation, Folsom, CA (May 2026–Present)

• Competitive research internship in Intel's XPU (accelerator) security division, selected following an invited talk at the Intel AI Forum on LLM-driven threat modeling for SoC security (Feb 2026). Focused on security research for next-generation accelerator architectures, working with Intel's AI and hardware security research community. Supervisor: James Cavanaugh, Intel.

Hardware Verification Engineer — XCelerium, Irvine, CA (via DSi, Bangladesh) (Jan 2022–Dec 2023)

• Verified custom RISC-V processor implementations at the ISA and system level using SystemVerilog, UVM, and cocotb — building familiarity with the hardware–software boundary where firmware executes and privilege/mode transitions occur.
• Verified AXI memory controllers and APB–AXI bridges, including CDC edge cases and assertion-based checks on bus-level access control — the same protocol surfaces targeted by firmware and software security assessments.
• Built Python-driven automation frameworks for coverage convergence, testbench orchestration, and results analysis, accelerating sign-off across multiple tapeout projects.